发明名称 SUB-RATE LOW-SWING DATA RECEIVER
摘要 A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.
申请公布号 US2015303920(A1) 申请公布日期 2015.10.22
申请号 US201213600534 申请日期 2012.08.31
申请人 Friedman Daniel J.;Liu Yong;Tierno Jose A. 发明人 Friedman Daniel J.;Liu Yong;Tierno Jose A.
分类号 H03K19/0185 主分类号 H03K19/0185
代理机构 代理人
主权项 1. A receiver adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing, the receiver comprising: a first sub-rate receiver block; and at least a second sub-rate receiver block, wherein a receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block; further wherein each of the first sub-rate receiver block and the second sub-rate receiver block comprises at least one gated-diode sense amplifier.
地址 Sleepy Hollow NY US