发明名称 ハードウェア設計のコンカレント及びシリアル混在型論理シミュレーション
摘要 <p>A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.</p>
申请公布号 JP5798132(B2) 申请公布日期 2015.10.21
申请号 JP20120556263 申请日期 2011.03.04
申请人 发明人
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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