发明名称 Semiconductor device
摘要 A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors. The first and fourth transistors are p-channel transistors. The second and fifth transistors are n-channel transistors. In the third and sixth transistors, an oxide semiconductor layer includes a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor. A low voltage is applied to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor.
申请公布号 US9165951(B2) 申请公布日期 2015.10.20
申请号 US201414190200 申请日期 2014.02.26
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Matsuzaki Takanori
分类号 H01L27/12;G02F1/1368;H01L27/06;G11C7/06;H01L29/786;G09G3/36;G02F1/1362 主分类号 H01L27/12
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein: the first transistor and the fifth transistor are p-channel transistors, the second transistor and the sixth transistor are n-channel transistors, the third transistor includes an oxide semiconductor layer including a channel formation region, the fourth transistor includes an oxide semiconductor layer including a channel formation region, the seventh transistor includes an oxide semiconductor layer including a channel formation region, the eighth transistor includes an oxide semiconductor layer including a channel formation region, a source of the first transistor is configured to be supplied with a high voltage, a source of the second transistor is configured to be supplied with a low voltage, a drain of the first transistor is electrically connected to a drain of the second transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor, a source of the fifth transistor is configured to be supplied with a high voltage, a source of the sixth transistor is configured to be supplied with a low voltage, a drain of the fifth transistor is electrically connected to a drain of the sixth transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor, a gate of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor, a gate of the second transistor is electrically connected to the other of the source and the drain of the third transistor, a gate of the fifth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and a gate of the sixth transistor is electrically connected to the other of the source and the drain of the seventh transistor.
地址 Atsugi-shi, Kanagawa-ken JP