Clamping of dynamic capacitance for graphics

摘要

Methods and apparatus relating to clamping or reducing of dynamic capacitance for graphics logic are described. In one embodiment, utilization values for a plurality of subsystems of a graphics logic are determined and a first capacitance value is in turn determined based on (e.g., a sum of products of) the determined utilization values (e.g., and one or more capacitance weight values). A second capacitance value (e.g., corresponding to a maximum dynamic capacitance or Cdyn_max corresponding to the graphics logic) is modified based on (e.g., a comparison of the first capacitance value and a (e.g., threshold) capacitance value. Other embodiments are also disclosed and claimed.

主权项

1. A processor comprising:
logic, at least a portion of which is in hardware, to determine utilization values for a plurality of subsystems of a graphics logic; logic, at least a portion of which is in hardware, to determine a first capacitance value based on the determined utilization values; and logic, at least a portion of which is in hardware, to cause modification to a second capacitance value, corresponding to the graphics logic, based on the first capacitance value and the second capacitance value, wherein logic to determine the first capacitance value is to determine the first capacitance value based on a sum of products of the determined utilization values and one or more capacitance weight values plus a baseline.