发明名称 Logical address translation
摘要 The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
申请公布号 US9164701(B2) 申请公布日期 2015.10.20
申请号 US201414255525 申请日期 2014.04.17
申请人 Micron Technology, Inc. 发明人 Culley Martin L.;Manning Troy A.;Larsen Troy D.
分类号 G06F12/00;G06F3/06;G06F12/02;G06F12/14;G06F12/04;G06F12/10 主分类号 G06F12/00
代理机构 Brooks, Cameron & Huebsch, PLLC 代理人 Brooks, Cameron & Huebsch, PLLC
主权项 1. A method for logical address (LA) translation, comprising: associating a first encryption key with a particular range of LAs and a second encryption key with a range of LAs outside the particular range, performing a write operation that includes skipping a number of physical locations corresponding to an offset such that data associated with the particular range of LAs is on a different page than data associated with the range of LAs outside of the particular range in response to the write operation including data associated with the first encryption key and data associated with the second encryption key; and translating the LA to a particular physical location in memory within the number of physical locations using the offset.
地址 Boise ID US