发明名称 Vertical bit line TFT decoder for high voltage operation
摘要 A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
申请公布号 US9165933(B2) 申请公布日期 2015.10.20
申请号 US201313788990 申请日期 2013.03.07
申请人 SanDisk 3D LLC 发明人 Rabkin Peter;Higashitani Masaaki
分类号 H01L27/105;H01L27/24;H01L27/115;G11C13/00;H01L45/00 主分类号 H01L27/105
代理机构 Vierra Magen Marcus LLP 代理人 Vierra Magen Marcus LLP
主权项 1. A non-volatile storage system, comprising: a substrate; a three dimensional memory array of memory cells positioned above the substrate; a plurality of word lines coupled to the memory cells; a plurality of global bit lines; a plurality of vertically oriented bit lines coupled to the memory cells; and a plurality of vertically oriented thin film transistor (TFT) select devices that are above the substrate, the vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines, when the vertically oriented TFT select devices are activated the vertically oriented bit lines are in communication with the global bit lines; each of the vertically oriented TFT select devices comprising: a first source/drain coupled to a first of the global bit lines;a second source/drain above the first source/drain and coupled to a first of the vertically oriented bit lines;a body having a first junction with the first source/drain and a second junction with the second source/drain;a gate having a top and a bottom relative to the substrate, either the first junction is below the bottom of the gate or the second junction is above the top of the gate; anda gate dielectric between the gate and the body.
地址 Milpitas CA US