| 发明名称 | Offset canceling dual stage sensing circuit | ||
| 摘要 | An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit. | ||
| 申请公布号 | US9165630(B2) | 申请公布日期 | 2015.10.20 |
| 申请号 | US201314015845 | 申请日期 | 2013.08.30 |
| 申请人 | QUALCOMM INCORPORATED;INDUSTRY-ACADEMIC COOPERATION FOUNDATION | 发明人 | Jung Seong-Ook;Na Taehui;Kim Jisu;Kim Jung Pill;Kang Seung Hyuk |
| 分类号 | G11C11/00;G11C11/16;G11C7/06;G11C13/00 | 主分类号 | G11C11/00 |
| 代理机构 | Seyfarth Shaw LLP | 代理人 | Seyfarth Shaw LLP |
| 主权项 | 1. A sensing method, comprising: in a first stage operation of a resistive memory sensing circuit, sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell; and in a second stage operation of the resistive memory sensing circuit, sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell. | ||
| 地址 | San Diego CA US | ||