发明名称 |
Multistage memory cell read |
摘要 |
A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read. |
申请公布号 |
US9165647(B1) |
申请公布日期 |
2015.10.20 |
申请号 |
US201414295512 |
申请日期 |
2014.06.04 |
申请人 |
Intel Corporation |
发明人 |
Guliani Sandeep;Pangal Kiran;Srinivasan Balaji;Hu Chaohong |
分类号 |
G11C13/00;G11C7/00;G11C13/02;G11C8/08;G11C16/26;G11C11/419;G11C11/56 |
主分类号 |
G11C13/00 |
代理机构 |
Vincent Anderson Law PC |
代理人 |
Vincent Anderson Law PC |
主权项 |
1. A method comprising:
charging a wordline of a memory device having a memory cell selected to read; enabling a global wordline driver that connects a global wordline path from the wordline to a sensing circuit that reads the memory cell, and enabling a local wordline driver that connects a local wordline path to the global wordline path; disabling the global wordline driver and maintaining enabled the local wordline driver; applying an initial voltage to a bitline of the selected memory cell; disabling the local wordline driver and maintaining disabled the global wordline driver; applying a higher voltage to the bitline; and enabling the global wordline driver and the local wordline driver to connect the memory cell to the sensing circuit to read the selected memory cell. |
地址 |
Santa Clara CA US |