Low power inverter circuit

摘要

A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

主权项

1. An inverter circuit, comprising:
a first transistor having a source terminal for receiving a supply voltage, and a gate terminal shorted to ground; a second transistor having a source terminal for receiving the supply voltage, and a drain terminal connected to a drain terminal of the first transistor; a first inverter, connected to the drain terminals of the first and second transistors, for receiving an input signal and generating an output signal at an output terminal; a third transistor having a drain terminal connected to the first inverter, a source terminal shorted to ground, and a gate terminal for receiving the supply voltage; a fourth transistor having a drain terminal connected to the drain terminal of the third transistor, and a source terminal shorted to ground; and a second inverter having an input terminal connected to the output terminal of the first inverter for receiving the output signal, and an output terminal connected to gate terminals of the second and fourth transistors.