Receiver with duobinary mode of operation

摘要

An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

主权项

1. An integrated circuit (IC) comprising:
a receiver including samplers to sample a signal and to generate a set of sampled signals; first logic to receive the set of sampled signals and operable to generate a binary output in dependence on simultaneous output of both samplers; and second logic to receive the set of sampled signals in parallel with the first logic and operable to generate a second binary output based on the output of one of the samplers only in dependence on feedback representing a prior symbol.