Reference-frequency-insensitive phase locked loop

摘要

A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

主权项

1. A method, comprising:in a phase locked loop:
generating, by the phase locked loop, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal, wherein the crystal clock signal is generated by a crystal in the phase locked loop; enabling, based on the generated reference clock signal, usage of both rising and falling edges of the crystal clock signal for an operation of the phase locked loop; performing the operation of the phase locked loop based on the enabling; and utilizing a sampled loop filter (SLPF) in the phase locked loop during the operating of the phase locked loop, wherein the sampled loop filter (SLPF) captures charge, at a frequency corresponding to the frequency of the reference clock signal, from a charge pump (CHP) in the phase locked loop.