发明名称 Method for fabricating nonvolatile memory device
摘要 A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.
申请公布号 US9165939(B2) 申请公布日期 2015.10.20
申请号 US201213606495 申请日期 2012.09.07
申请人 SK Hynix Inc. 发明人 Lee Nam-Jae
分类号 H01L21/8238;H01L21/76;H01L21/3205;H01L21/4763;H01L27/115;H01L27/06 主分类号 H01L21/8238
代理机构 IP & T Group LLP 代理人 IP & T Group LLP
主权项 1. A method for fabricating a nonvolatile memory device, comprising: forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region; forming a first isolation trench in the first region by selectively etching the first conductive layer, the first insulation layer, and the substrate of the first region; forming a first isolation layer filled in the first isolation trench; forming a second insulation layer and a conductive capping layer on the first isolation layer and the first conductive layer; etching the capping layer and the second insulation layer of the second region; forming a second conductive layer on a resultant structure; and forming first gate patterns by selectively etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region while forming a second isolation trench in the second region by selectively etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate of the second region, wherein the forming of the second isolation trench is performed after the forming of the first isolation trench, wherein the first region and the second region do not overlap with each other so that the first isolation trench of the first region does not overlap with the second isolation trench of the second region, and wherein the forming of the first gate patterns and the forming of the second isolation trench are completed at the same time.
地址 Gyeonggi-do KR