| 主权项 |
1. A system comprising:
a level 2 (L2) cache; and a processor coupled to the L2 cache, the processor comprising:
execution logic to support a virtual machine monitor;address space control registers to store a plurality of control bits, including a physical address extension bit and a no execution bit;a translation lookaside buffer (TLB) to store a plurality of page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages and address space identifiers (ASIDs), an ASID to identify an address space associated with corresponding PTEs, the ASID to match a value of a current ASID when the corresponding PTEs are loaded into the TLB; anda current ASID register to store the current ASID, the current ASID register to be updated on a context switch to a different address space;wherein, in response to the context switch and based on ASIDs of the PTEs and the current ASID stored in the current ASID register, the processor is to either not invalidate any PTEs of the TLB or to selectively invalidate one or more PTEs of the TLB;wherein, based on a first instruction to invalidate TLB entries corresponding to a specified address, the processor is to flush any TLB entries corresponding to that address, regardless of their ASID; andwherein, based on a second instruction, the processor is to transfer control from quest software to the virtual machine monitor. |
