发明名称 |
Decoupling bang-bang CDR and DFE |
摘要 |
An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. A phase detector of the bang-bang clock and data recovery module may be configured to eliminate coupling between the bang-bang clock and data recovery module and the decision feedback equalizer based upon an error signal of the decision feedback equalizer and a predetermined coefficient. |
申请公布号 |
US9166774(B2) |
申请公布日期 |
2015.10.20 |
申请号 |
US201012974601 |
申请日期 |
2010.12.21 |
申请人 |
Avago Technologies General IP (Singapore) Pte. Ltd. |
发明人 |
Zhong Lizhi |
分类号 |
H04L27/01;H04B1/02;H04L7/033;H04L25/03;H04L7/00 |
主分类号 |
H04L27/01 |
代理机构 |
Suiter Swantz pc llo |
代理人 |
Suiter Swantz pc llo |
主权项 |
1. An apparatus comprising:
a bang-bang clock and data recovery module; and a decision feedback equalizer, wherein a phase detector of said bang-bang clock and data recovery module is configured to generate a first output signal in response to a first data sample, a second data sample, and a crossing sample of a crossing between said first data sample and said second data sample and coupling between said bang-bang clock and data recovery module and said decision feedback equalizer is eliminated by subtracting a mathematical product of said first data sample, an error signal of the decision feedback equalizer, and a predetermined coefficient from said first output signal. |
地址 |
Singapore SG |