Memory interface circuitry with improved timing margins

摘要

Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.

主权项

1. Circuitry, comprising:
latch circuitry that receives a data strobe signal and a data strobe enable signal and latches the data strobe enable signal based on the data strobe signal; logic circuitry that receives the data strobe signal and the latched data strobe enable signal and produces a corresponding gated data strobe signal based on the latched data strobe enable signal; and control circuitry that generates a control signal by monitoring the gated data strobe signal, wherein the logic circuitry receives the control signal and produces the gated data strobe signal based at least partly on the control signal.