发明名称 Memory system components that support error detection and correction
摘要 The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. Moreover, the memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.
申请公布号 US9165621(B2) 申请公布日期 2015.10.20
申请号 US201414160290 申请日期 2014.01.21
申请人 Rambus Inc. 发明人 Perego Richard E.
分类号 G11C8/00;G06F11/10;G11C29/04 主分类号 G11C8/00
代理机构 代理人
主权项 1. A method of operating a memory device, the method comprising: receiving a write memory access command that specifies a write access of data and a write access of error information associated with the data at a memory bank within the memory device; receiving a base row address associated with the write memory access command; and generating first and second row addresses based on the base row address; wherein the write access of data accesses a first row in a first storage region of the memory bank based on the first row address; and wherein the write access of error information accesses a second row in a second storage region of the memory bank based on the second row address.
地址 Sunnyvale CA US