Methods and apparatuses for shifting data signals to match command signal delay

摘要

Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The clock generation circuit may be configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the clock signal. A delay path may be coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals. The delay path may be further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals. A driver may be coupled to the delay path and configured to receive the delayed data signal, and may further be configured to provide the delayed data signal to a bus.

主权项

1. An apparatus, comprising:
a clock generation circuit configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the input clock signal; a delay path coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals, the delay path further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals; and a driver coupled to the delay path and configured to receive the delayed data signal, the driver further configured to provide the delayed data signal to a bus, wherein the delay path comprises a plurality of latches coupled in series, each latch of the plurality of latches configured to receive one of the plurality of clock signals.