发明名称 |
Rule checking for confining waveform induced constraint variation in static timing analysis |
摘要 |
A method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for said each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for a timing constraint violation during the STA of the IC design according to the lookup table and re-optimizing the identified risky cell(s) is to reduce risk for the timing constraint violation of the IC design. |
申请公布号 |
US9165105(B2) |
申请公布日期 |
2015.10.20 |
申请号 |
US201414273724 |
申请日期 |
2014.05.09 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Hsu Meng-Kai;Chen Wen-Hao |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Duane Morris LLP |
代理人 |
Duane Morris LLP |
主权项 |
1. A computer-implemented method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design, comprising:
analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for each cell type according to a plurality of parameters for said each cell type; constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the cell library and is saved in a memory; identifying one or more cells in the IC design as risky for timing constraint violation(s) during the STA of the IC design according to the lookup table and; re-optimizing the identified risky cell(s) to reduce risk for the timing constraint violation(s) of the IC design. |
地址 |
Hsin-Chu TW |