Controlling an asymmetrical processor

摘要

In an embodiment, the present invention includes a multicore processor with a front end unit including a fetch unit to fetch instructions and a decode unit to decode the fetched instructions into decoded instructions, a first core coupled to the front end unit to independently execute at least some of the decoded instructions, and a second core coupled to the front end unit to independently execute at least some of the decoded instructions. The second core may have a second power consumption level greater than a power consumption level of the first core and also heterogeneous from the first core. The processor may further include an arbitration logic coupled to the first and second cores to enable the second core to begin execution responsive to a start processor instruction present in the front end unit. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a fetch unit to fetch instructions; a decode unit to decode the fetched instructions into decoded instructions; a first core coupled to the decode unit to independently execute at least some of the decoded instructions, the first core to operate at a first power consumption level; a second core coupled to the decode unit to independently execute at least some of the decoded instructions, the second core to operate at a second power consumption level greater than the first power consumption level, the second core heterogeneous from the first core; a memory order buffer and a result reorder buffer coupled to the first core and the second core; and an arbitration logic coupled to the first and second cores to control enablement of the second core.