| 发明名称 | Method of using a PMOS pass gate | ||
| 摘要 | A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC. | ||
| 申请公布号 | US9165640(B1) | 申请公布日期 | 2015.10.20 |
| 申请号 | US201414333871 | 申请日期 | 2014.07.17 |
| 申请人 | Altera Corporation | 发明人 | Liu Jun;Ratnakumar Albert;Rahim Irfan;Xiang Qi |
| 分类号 | G11C11/00;G11C11/412 | 主分类号 | G11C11/00 |
| 代理机构 | Mauriel Kapouytuan Woods LLP | 代理人 | Mauriel Kapouytuan Woods LLP ;Kapouytian Ararat |
| 主权项 | 1. A method comprising: using a p-channel metal oxide semiconductor (PMOS) pass gate to couple a first line to a second line, wherein a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell. | ||
| 地址 | San Jose CA US | ||