Semiconductor device incorporating a power on circuit

摘要

A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

主权项

1. A semiconductor device comprising:
a power on reset circuit outputting a power on reset signal from when supply voltage is turned on to when the supply voltage reaches a first threshold voltage; a setting section for setting a desired delay time; a signal generation circuit generating an internal reset signal by delaying the falling edge of the power on reset signal by the delay time set by the setting section; and an internal circuit reset by the internal reset signal.