发明名称 Gate signal line drive circuit and display
摘要 A gate signal line drive circuit and a display using the circuit, which suppress a leak current to reduce a power consumption. A gate signal line drive circuit that supplies a high voltage in a signal high period, and supplies a low voltage in a signal low period, the gate signal line drive circuit including: a high voltage supply switching element that turns on in response to the high period, supplies a voltage of a first basic clock signal to gate signal lines; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines in response to the signal low period.
申请公布号 US9166580(B2) 申请公布日期 2015.10.20
申请号 US201414250487 申请日期 2014.04.11
申请人 Japan Display Inc. 发明人 Miyamoto Motoharu;Ochiai Takahiro;Sato Hideo
分类号 H03K17/16 主分类号 H03K17/16
代理机构 Lowe Hauptman & Ham, LLP 代理人 Lowe Hauptman & Ham, LLP
主权项 1. A gate signal line drive circuit that supplies a high voltage to gate signal lines in a signal high period periodically repeated, and supplies a low voltage to the gate signal lines in a signal low period which is a period other than the signal high period, the gate signal line drive circuit comprising: a high voltage supply switching element that receives a first basic clock signal which becomes the high voltage in the signal high period at an input terminal thereof, turns on in response to the signal high period, supplies a voltage of the first basic clock signal to the gate signal lines, and turns off in response to the signal low period; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period to turn off the high voltage supply switching element; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines as the low voltage in response to the signal low period, and turns off in response to the signal high period, wherein the high voltage supply off control circuit comprises: a first high voltage supply off control element having an input terminal connected with a first voltage line, and an output terminal connected to the switch of the high voltage supply switching element; anda second high voltage supply off control element having an input terminal connected with a second voltage line, and an output terminal connected to the switch of the high voltage supply switching element, wherein the low voltage supply switching circuit comprises: a first low voltage supply switching element having an input terminal connected with a third voltage line, and an output terminal connected with the gate signal lines; anda second low voltage supply switching element having an input terminal connected with a fourth voltage line, and an output terminal connected with the gate signal lines, and wherein in a first period including two or more signal high periods sequentially coming, and starting from the signal low period, the first low voltage is supplied to the first voltage line, and the second low voltage is supplied to the third voltage line, the first high voltage supply off control element and the first low voltage supply switching element are in a drive on-state to turn on/off, and the second high voltage supply off control element and the second low voltage supply switching element are in a drive off-state to be kept in an off-state.
地址 Tokyo JP