High speed memory chip module and electronics system device with a high speed memory chip module

摘要

A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length.

主权项

1. A high speed memory chip module, comprising:
a type of memory cell array group, wherein the type of memory cell array group comprises multiple memory cell array integrated circuits (ICs), each of the memory cell array ICs has an input/output (I/O) data bus and at least one memory cell array corresponding to a first metal-oxide-semiconductor field-effect transistor (MOSFET) process, wherein the first MOSFET process corresponding to a first MOSFET gate length; and a logic unit for accessing the type of memory cell array group through a first transmission bus, wherein the first transmission bus is used for transmitting a first set of parallel data along with the memory cell array ICs, and bus width of the first transmission bus is wider than bus width of an I/O data bus of each of the memory cell array ICs, wherein the logic unit corresponds to a second MOSFET process, the second MOSFET process corresponds to a second MOSFET gate length, and the first MOSFET gate length is longer than the second MOSFET gate length; wherein the logic unit is further used for converting the first set of parallel data of the first transmission bus into a second set of parallel data through a second transmission bus.