Circuits, integrated circuits, and methods for interleaved parity computation

摘要

Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

主权项

1. An apparatus, comprising:
a parity circuit configured to determine a parity state of first and second command/address words in an interleaved manner based on first and second clock signals, wherein the first and second clock signals are out of phase with each other, provide respective asynchronous and synchronous signals based at least in part on the parity determination, and provide either an asynchronous alert signal to a component that supplied one of the first or second command/address words based on a combination of the two asynchronous signals or a synchronous parity error signal to a component incorporating the first and second command/address words based on a combination of the two synchronous signals, wherein the parity circuit is further configured to provide the asynchronous alert signal as a synchronous parity error signal to the component incorporating the first and second command/address words responsive to a select signal.