Lithium battery protection circuitry

摘要

A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.

主权项

1. A lithium battery protection circuit coupled to a lithium battery, comprising:
an over-charge protection circuit; a logic circuit coupled to over-charge protection circuit and having a first logic output and a second logic output; a level shift circuit coupled to the logic circuit through the first logic output and the second logic output and configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state; a substrate switching circuit coupled to the level shift circuit; and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode, wherein the level shift circuit includes:
a first inverter coupled to the second logic output;a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage;a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor;a first NMOS transistor coupled to the first logic output;a first transistor group, including a plurality of first group NMOS transistors connected in series, connected in parallel to a source and a drain of the first NMOS transistor;a second NMOS transistor coupled to the second logic output; anda second transistor group, including a plurality of second group NMOS transistors connected in series, connected in parallel to a source and a drain of the second NMOS transistor.