功率半导体器件及制备方法;A power semiconductor device and assembly method

摘要

本发明一般涉及一种半导体器件及其制备方法，更确切的说，本发明旨在提供一种集成有较小尺寸和薄型化晶片的功率半导体器件及其制备方法。提供一个包含多个基座的引线框架，将晶片粘附在本体部的顶面上，在晶片正面的各电极上植金属凸块，使各金属凸块的顶端凸出于引脚部的顶面所在的平面，加热金属凸块并利用一抵压板按压各金属凸块的顶端，使每个金属凸块所形成的平坦化的顶端面与所述引脚部的顶面齐平，切割引线框架分离各个基座。;This invention relates to power semiconductor device and the assembly method, more specifically the invention aims to provide a power semiconductor device integrating small size and thin chip and disclose a method of manufacturing this power device. Providing a lead-frame with a plurality of paddles, the chips are mounted to the upper surface of the body portion of the paddles, bumps are dropped and disposed on the electrodes arranged on the upper surface of the chip, and the top portion of the bump protrudes from a plane substantially coplanar to the upper surface of the lead portion of the paddle, then heating the bumps and pressing the top portion of the bump with a pressure-plate to flatten each of top portions of the plurality of bumps, so that the planarization top end-surface of top portion of the bump and the upper surface of the lead portion of the paddle are coplanar, afterwards the lead-frame is divided with a package saw process.