| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory element having soft error upset insensitivity.SOLUTION: A memory cell 18 includes: four inverter type circuits connected to a ring configuration; and four corresponding storage nodes. The four inverter type circuits form storage sections (X0, X1, X2, X3) of a memory cell. Some of the inverter type circuits includes tristate transistors in pull-up and pull-down paths. The tristate transistors are controlled by address signals. Addresses and access transistors are connected between some of the storage nodes and data lines. The addresses and access transistors are used to read memory cells and perform writing in the memory cells. |
