发明名称 SEMICONDUCTOR INTERCONNECT STRUCTURES
摘要 Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
申请公布号 US2015294935(A1) 申请公布日期 2015.10.15
申请号 US201514746315 申请日期 2015.06.22
申请人 INTEL CORPORATION 发明人 Boyanov Boyan;Singh Kanwal Jit;Clarke James;Myers Alan
分类号 H01L23/528;H01L23/522 主分类号 H01L23/528
代理机构 代理人
主权项 1. An integrated circuit device, comprising a conductive interconnect feature connecting to a first conductive feature, the conductive interconnect feature at least partially within a first insulator layer and passing through a conformal intervening layer distinct from the first insulator layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature does not penetrate the conformal intervening layer.
地址 Santa Clara CA US