发明名称 Data caching system and method for ethernet device
摘要 A data caching method for an Ethernet device is provided. The method includes: receiving data frames from various Ethernet interfaces and converting the Ethernet data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; maintaining a cache address in which data has already been written and a currently idle cache address in a cache; receiving the currently idle cache address and generating a write instruction and/or a read instruction for the cache and performing a write operation and/or a read operation so as to write the data received and processed by an IPC into the currently idle cache or to read data from the cache; and performing bit conversion and format encapsulation on the data that is read according to a read request and outputting the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface. A data caching system for an Ethernet device is also provided. By means of the data caching method and system provided herein, the expandability and the high bandwidth storage capacity of a network switching device can be improved, a high bandwidth utilization rate is achieved, and it becomes possible to improve bandwidth utilization rate based on traffic management.
申请公布号 US2015295859(A1) 申请公布日期 2015.10.15
申请号 US201314437904 申请日期 2013.10.21
申请人 ZTE CORPORATION 发明人 Yuan Feng
分类号 H04L12/931;H04L12/863;H04L29/12;H04L12/879 主分类号 H04L12/931
代理机构 代理人
主权项 1. A data caching system for an Ethernet device, the data caching system comprising: an input package process device IPC configured to receive data frames from various Ethernet interfaces, and convert the data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; a package address management device PMG configured to maintain a cache address in which data has already been written and a currently idle cache address in a cache; a memory control device MCT configured to receive the currently idle cache address from the PMG, generate a write instruction and/or a read instruction for the cache, and perform a write operation and/or a read operation to write the data received and processed by the IPC into an currently idle cache or to read data from the cache, wherein the read instruction and/or the write instruction are/is based on an internal read request and/or an internal write request of the system or are/is generated according to a read request received from the outside of the system; and an output package process device OPC configured to perform bit conversion and format encapsulation on the data that is read by the MCT based on the read request, and output the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface.
地址 Shenzhen, Guangdong CN