发明名称 WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY
摘要 To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.
申请公布号 WO2015084848(A3) 申请公布日期 2015.10.15
申请号 WO2014US68162 申请日期 2014.12.02
申请人 INVENSAS CORPORATION 发明人 WOYCHIK, CHARLES, G.;UZOH, CYPRIAN, EMEKA;CAO, ANDREW;SITARAM, ARKALGUD, R.
分类号 H01L23/00 主分类号 H01L23/00
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