发明名称 半導体装置の製造方法
摘要 <P>PROBLEM TO BE SOLVED: To make joining accuracy between respective regions higher, in division exposure for dividing a chip pattern into a plurality of regions, exposing the respective regions separately and joining the respective regions to each other. <P>SOLUTION: In the formation of an alignment mark for performing alignment, when divided pattern regions are exposed, at least one or more pairs of alignment marks in X and Y directions are provided in the vicinity of the circumference of the precedent divided exposure region, the following divided exposure region has a duplicate region including at least a pair of alignment marks being in the vicinity of the circumference of the precedent divided exposure region, and the process that the alignment is performed by an alignment mark coordinate viewed from the following exposure region is repeated to provide the alignment mark for all divided pattern regions of the chip pattern. Further, in the exposure of a superimposed layer, the alignment is performed with respect to the alignment mark for exposing each divided pattern region provided with high arrangement accuracy by using a die-by-die alignment method. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP5792431(B2) 申请公布日期 2015.10.14
申请号 JP20100102835 申请日期 2010.04.28
申请人 日本電気株式会社 发明人 遠山 茂
分类号 G03F9/00;H01L21/027 主分类号 G03F9/00
代理机构 代理人
主权项
地址