NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING

摘要

Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.