| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To increase efficiency in debugging. <P>SOLUTION: From a CPU 101, an accelerator 102 accepts a native instruction 112 of the accelerator 102, and information 113 specifying an intermediate instruction 111 associated with the native instruction 112. As a first instruction, the accelerator 102 accepts "NOT R3,1" as a native instruction 112-1, and "ldrp" as information 113-1. Then, as a second instruction, the accelerator 102 accepts "AND R3,R2,R3" as a native instruction 112-2, and "and" as information 113-2. Next, the accelerator 102 executes the native instructions 112 "NOT R3,1" and "AND R3,R2,R3", and records the information 113 "ldrp" and "and" specifying the intermediate instructions. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
