发明名称 動的バイナリ・トランスレータに関するメモリ管理のための装置、方法、およびコンピュータ・プログラム
摘要 <p>A dynamic binary translator apparatus, method and program for translating a first block of binary computer code intended for execution in a subject execution environment having a first memory of one page size into a second block for execution in a second execution environment having a second memory of another page size, comprising a redirection page mapper responsive to a page characteristic of the first memory for mapping an address of the first memory to an address of the second memory; a memory fault behaviour detector operable to detect memory faulting during execution of the second block and to accumulate a fault count to a trigger threshold; and a regeneration component responsive to the fault count reaching the trigger threshold to discard the second block and cause the first block to be retranslated with its memory references remapped by a page table walk.</p>
申请公布号 JP5792577(B2) 申请公布日期 2015.10.14
申请号 JP20110217087 申请日期 2011.09.30
申请人 发明人
分类号 G06F9/455;G06F12/14 主分类号 G06F9/455
代理机构 代理人
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