| 摘要 |
<p>The disclosed level conversion circuit has input circuitry 70, which may be an inverter, and which, in response to a transition of the input signal 72 between the higher and lower input levels, outputs a rising transition of a temporary output signal on the output line 74, towards the higher level of the input signal. Output control circuitry 80 detects the rising transition of the temporary output signal and pulls the output signal to the higher level of the output signal. This arrangement allows for fast level conversion without a DC leakage path as pull up transistor 78 of the input inverter is non-conductive. An isolating transistor 90 is present in an embodiment for cutting off the supply to the input inverter 70 once it has switched the output signal 74 to the level of the input voltage domain, so that it does not compete with the output control circuitry 80 which is pulling the output signal 74 to level of the output voltage domain. The circuit finds application in memory devices.</p> |
