发明名称 System and method for phase recovery with selective mitigation of timing corruption due to digital receiver equalization
摘要 A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.
申请公布号 US9160582(B1) 申请公布日期 2015.10.13
申请号 US201414230121 申请日期 2014.03.31
申请人 Cadence Design Systems, Inc. 发明人 Huss Scott;Moscone Chris;Vandersand, Jr. James
分类号 H04B1/10;H04L25/03 主分类号 H04B1/10
代理机构 Rosenberg, Klein & Lee 代理人 Rosenberg, Klein & Lee
主权项 1. A system for phase recovery of a signal received by a receiver having digital equalization comprising: a sample acquisition unit periodically acquiring over a series of predetermined unit intervals (UI) a plurality of in-phase (I) and quadrature (Q) samples of the received signal, each Q sample being disposed between consecutive I samples, said sample acquisition unit including a delay portion for selective mutual comparisons between a current I sample ID0, a first preceding I sample ID1, and a second preceding I sample ID2, wherein the ID0, ID1, ID2 samples are offset from one another by at least one UI; a transition detection unit coupled to said sample acquisition unit, said transition detection unit generating at least one transition detect signal responsive to the ID1 and ID0 samples and the Q sample disposed therebetween, the transition detect signal being indicative of a logic state transition in the received signal between the ID1 and ID0 samples; and, a transition filtering unit coupled to said sample acquisition and transition detection units, said transition filtering unit generating an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, said transition filtering unit actuating responsive to the equalization detect signal to selectively pass the transition detect signal to an output node; whereby corruption in the transition detect signal due to excessive equalization correction of the received signal at the ID0 sample is selectively mitigated.
地址 San Jose CA US