Memory device and method for measuring resistance of memory cell

摘要

A memory device includes a plurality of resistive memory units configured to receive a voltage of a corresponding line of a plurality of program/read lines, a plurality of switch units configured to each electrically connect a corresponding one of the resistive memory units with a corresponding line of a plurality of column lines in response to a voltage of a corresponding line of a plurality of row lines, where the program/read lines correspond to the row lines, respectively, a row control circuit configured to turn on the switch units by selecting at least one of the row lines and apply an external voltage to a program/read line corresponding to the selected row line in a first test mode, and a column control circuit configured to select at least one of the column lines and couple the selected column line with a ground voltage terminal in the first test mode.

主权项

1. A memory device, comprising:
a pad configured to receive an external voltage; a plurality of resistive memory units configured to receive a voltage of a corresponding line of a plurality of program/read lines; a plurality of switch units configured to each electrically connect a corresponding one of the resistive memory units with a corresponding column line of a plurality of column lines in response to a voltage of a corresponding row line of a plurality of row lines, where the program/read lines correspond to the row lines, respectively; a row control circuit configured to turn on the switch units by selecting at least one of the row lines and apply the external voltage to a program/read line corresponding to the selected row line in a first test mode; and a column control circuit configured to select at least one of the column lines and couple the selected column line with a ground voltage terminal in the first test mod;
wherein the column control circuit comprises:a column decoder configured to connect the selected column line with a first node;a current limiter configured to limit current from the first node to the ground voltage terminal in response to a bias voltage;a bias voltage supplier configured to generate the bias voltage such that the current limiter is completely turned on in the first test mode and the current limiter has a resistance appropriate for a read operation in a normal mode; anda sense amplifier configured to sense data by comparing a voltage of the first node with a reference voltage.