Memory devices and their operation with different sets of logical erase blocks

摘要

Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria.

主权项

1. An electronic system, comprising:
a processor configured to manage storage of data to different portions of memory cells based on a programmable, predetermined criteria; and one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises: the array of memory cells, wherein the memory array is organized into a plurality of erasable physical blocks and has a first erasable logical block that is smaller than a second erasable logical block; a control register storing an address of the array of memory cells, wherein the address is indicative of at least one of a starting address and an ending address for physical blocks associated with a particular portion of the array of memory cells having a particular logical erase block size.