SRAM bitcell implemented in double gate technology

摘要

An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

主权项

1. A static random access memory (SRAM) bitcell circuit, comprising:
a first CMOS inverter having a first input and a first output and formed by a first p-channel transistor and a first n-channel transistor; a second CMOS inverter having a second input and a second output and formed by a second p-channel transistor and a second n-channel transistor; wherein the first output is coupled to the second input at a true node; wherein the second output is coupled to the first input at a complement node; a first pass transistor coupled between a true bitline node and the true node; a second pass transistor coupled between a complement bitline node and the complement node; a first direct connection of the true bitline node to apply a true bitline potential to a back gate of the second p-channel transistor in the second CMOS inverter; and a second direct connection of the complement bitline node to apply a complement bitline potential to a back gate of the first p-channel transistor in the first CMOS inverter.