发明名称 Electronic device and semiconductor device
摘要 There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.
申请公布号 US9158717(B2) 申请公布日期 2015.10.13
申请号 US201514696372 申请日期 2015.04.24
申请人 Renesas Electronics Corporation 发明人 Yoshikawa Yasuhiro;Suwa Motoo
分类号 H01L23/48;G06F3/00;G06F13/28;G11C7/10;H05K1/02;G06F13/40;H01L23/498 主分类号 H01L23/48
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. An electronic device comprising: (a) a mounting board; (b) a first semiconductor device mounted over the mounting board, wherein the first semiconductor device includes: a first wiring substrate,a first semiconductor chip mounted over a chip mounting surface of the first wiring substrate, anda plurality of external terminals electrically connected with the first semiconductor chip and also formed on a mounting face opposite to the chip mounting surface of the first wiring substrate; and (c) a second semiconductor device mounted over the mounting board, wherein the second semiconductor device is electrically connected with the first semiconductor device, wherein the second semiconductor device includes: a second wiring substrate,a second semiconductor chip mounted over a chip mounting surface of the second wiring substrate, anda plurality of external terminals electrically connected with the first semiconductor device and formed on a mounting face opposite to the chip mounting surface of the second wiring substrate, wherein, in plan view, the plurality of external terminals of the first semiconductor device are formed in a plurality of rows and arranged along each edge of the mounting face of the first wiring substrate, wherein the plurality of external terminals of the first semiconductor device include: a first external terminal group arranged at a peripheral portion of the mounting face of the first wiring substrate, anda second external terminal group arranged further than the first external terminal group from each edge of the mounting face of the first wiring substrate, wherein, in plan view, an interval between the first external terminal group and the second external terminal group is larger than a diameter of each of the plurality of external terminals, wherein the first semiconductor device is mounted over the mounting board such that a first edge of edges of the mounting face of the first wiring substrate faces the second semiconductor device, wherein the plurality of external terminals of the first semiconductor device include a plurality of interface terminals electrically connected with the second semiconductor device, wherein the plurality of interface terminals are arranged along the first edge of the mounting face of the first wiring substrate, wherein the plurality of interface terminals comprise multiplexed terminals, including a first interface terminal group, a second interface terminal group and a third interface terminal group, having different signal input/output configurations from each other, wherein the first interface terminal group, the second interface terminal group and the third interface terminal group are distributed to the first external terminal group and the second external terminal group, wherein, in plan view, the second interface terminal group is arranged between the first interface terminal group and a second edge intersecting with one end part of the first edge, wherein, in plan view, the third interface terminal group is arranged between the first interface terminal group and a third edge intersecting with the other end part of the first edge, wherein the first semiconductor device is a baseband processor that provides specified communication protocol control for the electronic device, wherein the second semiconductor device is a synchronous dynamic random-access memory (DRAM), wherein each of the second interface terminal group and a first part of the first interface terminal group is assigned one of signal uses for a command/address-based terminal function and a data-based terminal function of memory without duplication, and wherein each of the third interface terminal group and a second part of the first interface terminal group is assigned the other of signal uses for the command/address-based terminal function and the data-based terminal function of memory without duplication.
地址 Tokyo JP