Data processing device and method, and processor unit of same

摘要

A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs.

主权项

1. A data processing device comprising an external memory that stores an instruction and data necessary for execution of the instruction and a plurality of processor units,
each of the plurality of processor units comprising: cache memory that temporarily stores the instruction and the data; an instruction execution unit that reads the instruction and the data from the external memory via the cache memory and executes the instruction; an initiation detecting unit that detects an entering of a thread implemented by processing of the instruction execution unit into an exclusive control section, which is specified in advance to become a bottleneck; and a termination detecting unit that detects an exiting of the thread out of the exclusive control section, and wherein each of the plurality of processor units leaves, in the cache memory, data used in the exclusive control section when determining a replacement target of cache entries due to a fact that the memory access of the instruction execution unit results in a cache miss.