Fin sidewall removal to enlarge epitaxial source/drain volume

摘要

A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

主权项

1. An integrated circuit that includes one or more FinFET devices, a FinFET device comprising:
a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface; a fin of semiconductor material extending upwards from the substrate through an opening in the dielectric layer, wherein a base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions, and wherein an upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface; a gate electrode straddling the upper channel region and being separated from the upper channel region by a gate dielectric; and first and second epitaxial source/drain regions that meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively, wherein the first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.