| 发明名称 | Transistor and method of manufacturing the same | ||
| 摘要 | A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. | ||
| 申请公布号 | US9159827(B2) | 申请公布日期 | 2015.10.13 |
| 申请号 | US201414322094 | 申请日期 | 2014.07.02 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Cheng Chih-Chang;Chu Fu-Yu;Liu Ruey-Hsin |
| 分类号 | H01L29/78;H01L29/41;H01L21/336;H01L29/40;H01L29/66;H01L21/28;H01L29/417;H01L29/423;H01L29/08 | 主分类号 | H01L29/78 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A method of forming a manufacture, the method comprising: forming a first trench in a doped layer, the first trench having an upper portion and a lower portion, a width of the upper portion being greater than a width of the lower portion; forming a first insulating layer along sidewalls of the lower portion of the first trench and a bottom surface of the first trench; forming a gate dielectric layer along sidewalls of the upper portion of the first trench; forming a first conductive feature along sidewalls of the gate dielectric layer; forming a second insulating layer covering the first conductive feature and the first insulating layer; and forming a second conductive feature along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. | ||
| 地址 | TW | ||