Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof

摘要

The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

主权项

1. A non-volatile resistive memory device, comprising:
a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines; a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines, wherein each of the memory cells comprises:
a cell selecting transistor having a source, a drain and a gate;a resistive memory element serially connected to a drain-source path of the cell selecting transistor,wherein the resistive memory element and the cell selecting transistor are configured to form a conductive path between one of the bit lines and one of the source lines, andwherein the gate of the cell selecting transistor is connected to one of the word lines; and a boosting capacitor having a first electrode and a second electrode,
wherein the first electrode of the boosting capacitor is connected to one of the form lines,wherein the second electrode of the boosting capacitor is connected to an internal node of each of the memory cells, the internal node formed at a connection point between the resistive memory element and the cell selecting transistor,wherein the boosting capacitor is configured to supply a boosting voltage to the internal node, andwherein a dielectric material of the boosting capacitor and a dielectric material of the resistive memory element are formed of the same dielectric material.