Phase interpolator

摘要

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

主权项

1. A phase interpolation device comprising:
a positive power supply terminal; a negative power supply terminal; and a first interpolation core comprising: a positive in-phase cascode current source having a positive in-phase input coupled to the positive power supply terminal through a programmable positive in-phase control, and having a positive in-phase output coupled to a first common node; a positive quadrature phase cascode current source having a positive quadrature phase input coupled to the positive power supply terminal through a programmable positive quadrature phase control, and having a positive quadrature phase output coupled to the first common node; a negative in-phase cascode current source having a negative in-phase input coupled to the negative power supply terminal through a programmable negative in-phase control, and having a negative in-phase output coupled to the first common node; and a negative quadrature phase cascode current source having a negative quadrature phase input coupled to the negative power supply terminal through a programmable negative quadrature phase control, and having a negative quadrature phase output coupled to the first common node; a second interpolation core having a second common node; a comparator having a plus terminal, a negative terminal, and a phase interpolation output; wherein the plus terminal of the comparator is coupled to the first common node; and wherein the negative terminal of the comparator is coupled to the second common node.