发明名称 Semiconductor memory device
摘要 A semiconductor memory device includes a sense amplifier, and the sense amplifier includes a bus, first and second latch circuits, and a third transistor. The first latch circuit includes a first transistor connected to the bus, and the second latch circuit includes a second transistor connected to the bus. When data is transmitted from the first latch circuit to the second latch circuit, a third transistor is switched on to precharge the bus by applying a first voltage that is lower than a power source voltage of the first and second latch circuits to a gate of the third transistor. Thereafter, second and third voltages that are lower than the power source voltage are applied to gates of first and second transistors, respectively.
申请公布号 US9159439(B2) 申请公布日期 2015.10.13
申请号 US201314013833 申请日期 2013.08.29
申请人 Kabushiki Kaisha Toshiba 发明人 Maejima Hiroshi
分类号 G11C16/06;G11C16/26;G11C11/56;G11C16/04;G11C16/08 主分类号 G11C16/06
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A semiconductor memory device comprising: a memory cell array that includes multiple memory cells that are stacked above a semiconductor substrate; and a sense amplifier that can retain data read from or to be written to a memory cell, the sense amplifier including a bus that can transmit the data, a first latch circuit that includes a first data retention unit and a first transistor connecting the first data retention unit and the bus, a second latch circuit that includes a second data retention unit and a second transistor connecting the second data retention unit and the bus, and a third transistor, wherein when the data is transmitted from the first latch circuit to the second latch circuit, the third transistor is switched on to charge the bus to an electric potential lower than a power source voltage of the first and second latch circuits, by applying a first voltage lower than the power source voltage to a gate of the third transistor, and after precharging the bus, second and third voltages that are lower than the power source voltage, are applied to gates of the first and second transistors, respectively.
地址 Tokyo JP