Memory array clock gating scheme

摘要

Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.

主权项

1. A processing device, comprising:
a processing component that receives a system clock signal and is operable to process instructions synchronously with the system clock signal; a memory component coupled to the processing component through a memory control interface, the memory component receiving the system clock signal and including a sequential element physically laid out in a manner that registers a memory control signal of the memory control interface based on a gated system clock signal; and a clock gating element that receives the system clock signal and a clock gate enable signal, the clock gating element controlled by the clock gate enable signal to generate the gated system clock signal, the clock gate enable signal coupled to the processing component, wherein the processing component processes an instruction associated with the memory control signal, in response to the memory control signal having previously been identified to not meet a minimum setup time associated with clock-gating the memory control signal, to: identify a clock gating location prior to an execution stage of an instruction processing sequence that is upstream of the memory control signal by an amount that satisfies the minimum setup time without modifying the physical layout of the sequential element; and generate a clock enable value for the clock gate enable signal associated with the instruction at the clock gating location.