发明名称 |
Process for manufacture of super lattice using alternating high and low temperature layers to block parasitic current path |
摘要 |
A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps. |
申请公布号 |
US9157169(B2) |
申请公布日期 |
2015.10.13 |
申请号 |
US200611531508 |
申请日期 |
2006.09.13 |
申请人 |
International Rectifier Corporation |
发明人 |
Bridger Paul;Beach Robert |
分类号 |
C30B25/02;C30B23/00;C30B29/40;H01L33/04;C30B23/06;C30B25/10;C30B25/16;H01L21/02 |
主分类号 |
C30B25/02 |
代理机构 |
Farjami & Farjami LLP |
代理人 |
Farjami & Farjami LLP |
主权项 |
1. A method of fabricating a power field-effect transistor (power FET), comprising:
providing a substrate; growing a III-nitride body comprising aluminum nitride (AlN) over a major surface of said substrate to a final thickness over a growth period of time, wherein growth temperature is started at a low growth temperature and varied in cycles thereafter over said growth period of time, each cycle including a period of high temperature growth at a high temperature and a period of low temperature growth at a low temperature; said high temperature and said low temperature converging during said growth period of time until said high temperature and said low temperature are substantially equal to a final growth temperature of said III-nitride body; said III-nitride body being a superlattice structure wherein a number of layers grown at said high temperature is equal to a number of layers grown at said low temperature; forming a buffer layer over said III-nitride body; forming an active layer on said buffer layer, said active layer providing an active region for said power FET; said buffer layer and said III-nitride body being provided to resist current flow outside said active layer. |
地址 |
El Segundo CA US |