Efficient, programmable and scalable low density parity check decoder

摘要

Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

主权项

1. A low density parity check decoder comprising:
a plurality of message processing blocks arranged in a logical array; a plurality of info bit processors, one for each column of said message processing blocks in said logical array; a plurality of lookup table memories, one for each column of said message processing blocks in said logical array; and a plurality of check message processors, one for each row of said message processing blocks in said logical array, wherein said decoder iteratively operates to decode a data signal, and wherein the lookup table memories are loaded with: information as to which bits of a corresponding compressed parity matrix are set to 1, said corresponding compressed parity matrix having an equal number of columns as the plurality of lookup table memories.