Controlled on and off time scheme for monolithic cascoded power transistors

摘要

A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.

主权项

1. A semiconductor device, comprising:
a depletion mode gallium nitride field effect transistor (GaN FET) in which a drain of said depletion mode GaN FET is coupled to a drain terminal of said semiconductor device; an n-channel metal oxide semiconductor (NMOS) transistor configured to operate in an enhancement mode, in which a drain of said NMOS transistor is coupled to a source of said depletion mode GaN FET; and a gate network which independently controls a turn-on time and a turn-off time of said depletion mode GaN FET in conjunction with a gate to drain capacitance of the GaN FET, said gate network being coupled to a gate of said depletion mode GaN FET, a source of said NMOS transistor and a gate of said NMOS transistor.